Generally, de-embedding is the extraction of parasitic behaviors of components in an electrical network to determine the electrical behavior of a particular component within the electrical network. By extracting the parasitic values from a measured behavior of the network, the particular component may be isolated from the remainder of the network and evaluated independently. De-embedding is particularly useful in the semiconductor industry to isolate a structure within an integrated circuit to determine if the structure is operating correctly, such as during wafer acceptance testing (WAT). For example, during WAT, it may be desirable to extract parasitics caused by pads, interconnects, and transmission lines from a network that also includes a device under test (DUT) to analyze the DUT independently from the network.
Typical de-embedding techniques generally require measuring the behavior of the network, determining some representation of the network such as by parameters that are known in the art, using equivalent circuits to model parasitics in components, and using mathematical manipulations of the representation of the network and the model to determine the behavior of the desired component.
However, these techniques may suffer from disadvantages. A disadvantage is that the model used may become invalid when electrical properties of the networks cannot be modeled by an equivalent circuit or that an accurate equivalent circuit would be difficult to obtain or use, such as if interconnect or transmission lines lengths become too long or the operating frequency becomes too high. Another disadvantage is that the model may assume that a ground strip typically used in a structure may have negligible effects on the electrical properties of the structure. The model may ignore these effects that may be significant at high frequencies which may result in over de-embedding. Accordingly, there is a need in the art to overcome these disadvantages.